The present invention relates generally to integrated circuit devices, and more specifically to integrated circuit devices which have fuse circuitry as a programming means.
A variety of integrated circuit devices, including memories and microprocessors, utilize fuse programming circuitry. For instance, integrated circuit memories have addressable elements which must be replaced by redundant elements free from defect when the addressable elements are faulty in some way. Addressable and redundant elements of an integrated circuit may be defective for a number of reasons well known in the art, such as particle contamination, bit defects, locked rows, and locked columns. An integrated circuit memory, for example, has a plurality of addressable elements, such as rows and columns, and a plurality of redundant elements which may be used to replace defective addressable elements if the redundant elements, themselves, are free of defects. Thus, typically prior to laser repair, it would be desirable to enable and test redundant elements in order to ascertain that the redundant elements are free of defects and therefore suitable for replacing defective addressable elements. Redundant elements are enabled prior to laser repair so that it may be determined whether each redundant element is free of defects and therefore suitable for replacement of defective rows and columns.
Circuitry used to enable redundant elements of an integrated circuit typically has fuse circuitry which controls whether the redundant element will be enabled. Typical fuse circuits are shown in FIGS. 1a and 1b, and these circuits are frequently used to provide master enabling control of redundant elements. Referring to fuse circuitry 10 of FIG. 1a, if fuse 12 is intact, OUT signal 18, after passing through inverters 16 and 17, is a high logic level; if fuse 12 is blown, OUT signal 18 is a low logic level, due to junction leakage and transistor conduction to VSS or ground. OUT signal 18 is connected to redundant element 19 which is enabled when fuse 12 is blown and OUT signal 18 is a logic low level Similarly for fuse circuitry 20 of FIG. 1b, if fuse 22 is intact, OUT signal 28, after passing through inverters 26 and 27, is a low logic level; if fuse 22 is blown, OUT signal 28 is a high logic level, due to junction leakage and transistor conduction to VCC. OUT signal 28 is connected to redundant element 29 and determines whether redundant element 29 will be enabled. When fuse 22 is blown, OUT signal 28 is a high logic level and redundant element 29 is enabled.
It would be desirable to use fuse circuitry similar to that shown in FIGS. 1 a and 1b to temporarily enable and then test a redundant element to determine whether it is defective prior to laser repair. Those redundant elements which are found to be defective are logged during laser repair and may be subsequently bypassed and not used to replace a defective addressable element. For example, a defective addressable element may be replaced by two redundant elements, redundant element X and redundant element Y, either one of which may be used to replace the defective addressable element. Using the fuse circuitry described above, it would be desirable to determine prior to laser repair that redundant element X is defective. This information is logged during laser repair so that the defective addressable element is replaced with redundant element Y rather than defective redundant element X.
The circuitry of FIGS. 1 a and 1b may be used to control logic gates, as shown in FIG. 2, or to provide multiplexing control, as shown in FIG. 3. Referring to FIG. 2, decoder circuitry 30 employs fuse circuitry 31, which is analogous to fuse circuitry 20 of FIG. 1b and is comprised of fuse 32, transistor 34, and inverters 36 and 38, in order to control passgates 48 and 50. Fuse circuitry 31 produces signal 40 which controls passgates 48 and 50 as shown. Signal 40 controls the p-channel transistor and the n-channel transistor of passgates 48 and 50, respectively. Signal 47 is the inverse of signal 40 and is produced after passing through inverter 46; signal 47 controls the n-channel transistor and the p-channel transistor of passgates 48 and 50, respectively. Addressi' is generated by passgates 48 and 50 as determined by fuse circuitry 31. When fuse 32 is blown, addressi signal 42 is passed through passgate 50, non-inverted, as addressi' signal 52. When fuse 32 is left intact, addressi signal 42 is passed through passgate 48, inverted, as addressi' signal 52. The circuitry so far described is represented by circuitry 57 which is contained within the dashed lines of FIG. 2. Circuitry 57 only performs logic on addressi signal 42, and thus must be duplicated for each of signals addressj, addressk, not shown, in order to produce addressj' signal 54 and addressk' signal 56.
Addressi' signal 52, addressj' signal 54, and addressk' signal 56 are address input signals to NAND gate 68 as shown. Fuse circuitry 65, comprised of master fuse 58, transistor 60, and inverters 62 and 64, is used to enable or disable NAND gate 68. When master fuse 58 is blown, NAND gate 68 is enabled and generates redundant select signal 70 as a function of the address sequence addressi, addressj, addressk, etc. programmed in. Redundant select signal 70 connects to a given redundant element 72, such as a word line which is defined by the address sequence which was programmed in. However, if master fuse 58 is not blown, NAND gate 68 is not enabled and redundant select signal 70 is locked to a high logic level.
Referring to FIG. 3, multiplexing circuitry 80 employs fuse circuitry 82, which is analogous to fuse circuitry 10 of FIG. 1a. Fuse circuitry 82 controls the enabling of redundant element 106 and is comprised of fuse 84, transistor 86, and inverters 88 and 90. Address signals 91a to 91h are input signals to passgates 92a to 92h, respectively, as shown and may be true and complement signals. For example, address signals 91a and 91b may be the complement of each other. The output signals of passgates 92a and 92b pass through fuses 93a and 93b, respectively, before being connected together to form signal 94; the output signals of passgates 92c and 92d pass through fuses 93c and 93d before being connected together to form signal 96; the output signals of passgates 92e and 92f pass through fuses 93e and 93f before being connected together to form signal 98; and the output signals of passgates 92g and 92h pass through fuses 93g and 93h before being connected together to form signal 100. Signals 94, 96, 98, and 100 are input signals to NAND gate 102.
Fuse circuitry 82 controls passgates 92 which in turn control the generation of Redundant Element Select signal 104. Thus, fuse circuitry 82 controls whether multiplexing circuitry 80 is enabled. When fuse 84 of fuse circuitry 82 is blown, passgates 92 are enabled, one of the two fuses 93 associated with each NAND gate input signal 94, 94, 98, or 100 are blown, and the n-channel transistor 95 is off and allows either a true or complement address signal 91, depending on which fuse 93 is blown, to propagate to NAND gate 102 such that Redundant Element Select signal 104 may ultimately be produced. However, when fuse 84 is not blown and is left intact, passgates 92 are not enabled and therefore do not pass through an address signal 91. N-channel transistor 95 pulls the input signal 94, 96, 98, or 100 of NAND gate 102 to a predetermined logic state so that it does not float. As a result, Redundant Element Select signal 104 is never generated and redundant element 106 is not enabled.
FIGS. 2 and 3 illustrate how conventional fuse circuitry 31, 65, and 82, respectively, may be used to provide master enabling control of redundant elements. Enabling of redundant elements is desirable prior to laser repair to ensure that only redundant elements free from defects are used to replace defective rows and/or columns. Unfortunately, the fuse circuitries 10, 20, 31, 65, and 82 of FIG. 1a, 1b, 2, and 3, respectively, require that the enabling and/or testing of redundant elements be performed in a permanent manner, in that a fuse must actually be blown. This process is not reversible. In other words, a fuse which is connected to a first or a second power supply, VCC or VSS, must be blown or not blown in order to provide master enabling control of redundant elements.